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ProjectA semester of eveningsAbout $215 for two assembled eight-channel boardsTier 2

Project A: The ADS1299 board

Eight channels of 24-bit EEG around the chip inside most research and consumer systems. Schematic in KiCad, fabricated and assembled by JLCPCB, firmware on an ESP32, streaming into BrainFlow. A semester of evenings, and the whole signal chain becomes yours.

AssumesProject B: One channel of youKiCad to JLCPCBFirmware and SPI for a biopotential chipSpineAnalog / mixed-signal hardware
On this pageA semester of evenings
  1. The design, stage by stage
  2. Bring-up, in order
  3. The registers you will actually set
  4. Where this leads

Your one-channel amplifier is three chips, two batteries, and a mat of jumper wires, and it picks up the room whenever you move your elbow. It gave you one trace. To see alpha move across the back of the head, or to tell a left hand from a right one, you need eight of it, quieter, on something that does not fall apart when the desk is bumped.

All of that fits in a 10 mm square. The Texas Instruments holds eight , eight 24-bit converters, a amplifier, lead-off detection, and a test-signal generator. It is inside the Cyton, inside several clinical amplifiers, and inside more than one consumer headset. Building a board around it is the audition for the hardware spine. You draw the schematic, lay out the board, have it made and assembled for about $215, write the that configures it and streams samples, and end up with an instrument whose every design decision you can defend.

Figure 1. One channel, from scalp to microcontroller. Everything between the jack and the SPI pins is inside the chip, and there are eight of it. The breadboard version of this took you three chips and most of an evening to get working once.
Predict before you look

The ADS1299's reference is 4.5 V and its maximum gain is 24. At that gain, how big is one step of the 24-bit converter?

About 22 nanovolts. Full scale is ±4.5 V divided by the of 24, so ±187.5 mV, or 375 mV total. Divide by 2²⁴ (about 16.8 million) and each step is 22.4 nV. The chip’s own noise is around a microvolt, so the last five bits or so are noise. That is normal for a delta-sigma converter and it is why “24-bit” is a description of the arithmetic, not the accuracy. The explainer on analog to digital is about this.

Parts

PartWhereQtyApprox.
ESP32 DevKit (or Raspberry Pi Pico)
For streaming from the ADS1299 board over USB later. Either board works; pick one ecosystem and learn it.
Amazon, Adafruit, SparkFun1$9
Temperature-adjustable soldering iron kit with solder, stand, and flux
$11.99 for the iron, five tips, solder, a stand, and flux, which is everything Phase 1 needs. Its temperature dial is open-loop and its tips wear fast; the Pinecil V2 at $25.99 from Pine64 holds temperature properly and will outlast your degree, and it needs a USB-C PD supply you may already own.
Amazon1$12
Handheld oscilloscope with a built-in signal generator (FNIRSI DSO-510)
$44.99 for 10 MHz, 48 MSa/s, and a DDS generator in one box, which replaces two purchases. 10 MHz is plenty for biopotentials and enough to eyeball SPI, but not enough for careful digital timing; the engineering building has real bench scopes for that. A Hantek 6022BE USB scope is $65.90 and a Rigol DHO800 is the one to want.
Amazon1$45
USB isolator (ADuM3160 based)
Lets the board talk to a laptop on charger power without connecting the laptop's ground to you. It is full-speed only (12 Mbps), which is fine here. Adafruit's is $34.95 with better isolation ratings and documentation. Batteries are still simpler.
Amazon1$9
Your ADS1299 board, fabricated and assembled by JLCPCB (5 boards, 2 assembled)
The chip dominates. The eight-channel ADS1299IPAG is $69.82 each from TI in single quantity. JLCPCB's own charges are small (bare boards about $2, an $8.18 economic assembly setup, a $1.53 stencil, $0.0016 per joint); the rest is the other components and shipping. The four-channel ADS1299-4PAGR is $37.10 at LCSC and brings the whole order to about $150, and four channels cover every Phase 3 project. Order two assembled so one can die.
JLCPCB1$215
Total (prices drift; treat as a ceiling)$290

The design, stage by stage

Start from TI’s evaluation board schematic and the Cyton schematic, both public. Do not invent; copy and understand, then change one thing at a time.

Figure 2. Where things sit, and why. The line down the middle is the only layout decision that really matters: digital return currents take the short way home, and the short way home must not run under the input traces.

Power. A 5 V analog rail (AVDD) from a low-noise regulator and a 3.3 V digital rail (DVDD) for the chip’s logic and the microcontroller. If your microcontroller is a 3.3 V part, DVDD at 3.3 V means no level shifting. The Cyton runs the analog side at ±2.5 V instead of 0 to 5 V; either works. Every supply pin gets a 0.1 µF capacitor within a few millimetres, and the reference pins get the capacitors the specifies to the microfarad.

Inputs. Each channel is a differential pair. For you usually tie all the negative inputs together to a single through the chip’s SRB pin, so each channel measures its against the common reference. A small series resistor (a few kilohms) and a capacitor on each input give input protection and some radio-frequency filtering. Connect through touch-proof (DIN 1.5 mm) sockets so that ordinary plug straight in.

Bias drive. The chip’s BIAS amplifier is the you built by hand in Phase 1, now built in. Its output goes through the series resistor to a third . The internal bias reference can be set to mid-supply.

Digital. to the microcontroller: clock, data in, data out, chip select, plus the data-ready line that the chip pulls low each time a sample is available, and start and reset lines. Keep the digital traces away from the analog inputs.

Layout. Analog on one side, digital on the other, one ground plane split logically so digital return currents never cross under the analog inputs. Input traces short, paired, and symmetric. A guard ring around the input section. The ’s layout section is short and every sentence in it is there because someone got it wrong.

Assembly. The is a 64-pin quad flat pack with 0.5 mm pitch. You can hand-solder it with flux and patience, but will place and solder it for a few dollars, and the chip is expensive enough that you want the reflow done by a machine. Order the passives from their parts library so everything can be assembled in one go.

Bring-up, in order

  1. Before the chip is powered, check every supply rail with the multimeter with the microcontroller disconnected. 5.0 on AVDD, 3.3 on DVDD, nothing shorted.
  2. Connect the microcontroller. Read the ID register over . The returns a fixed value (0x3E) and until you read it, nothing else matters. If you cannot, check chip select polarity, mode (the chip wants clock polarity 0, phase 1), and that the clock is running.
  3. Turn on the internal test signal (a square wave of known amplitude) and route it to all channels. Read data frames on each data-ready pulse: 3 status bytes then 8 × 3 bytes of channel data, two’s complement. Convert to volts. You should see the square wave at exactly the ’s amplitude on every channel. This validates the , the framing, the sign handling, and the scaling in one step.
  4. Short all inputs to the bias reference on the board and record sixty seconds at 24 and 250 samples per second. Compute the RMS in 0.5 to 40 Hz. This is your ; a good board is around 1 µV RMS. Write it down. It is the first number on your report.
  5. Connect : eight on the head or two for a start, reference to SRB, bias to the forehead. Run the eyes-closed test. Alpha, on eight channels, from a board you designed.
  6. Stream to the computer over Wi-Fi or Bluetooth using the Cyton’s serial protocol, so that and every tool that speaks to a Cyton speaks to your board too. Or write your own simple protocol and a small Python receiver. Then wrap it as a outlet.
Figure 3. One sample, as the chip hands it over. Twenty-seven bytes, 250 times a second, most significant byte first, two's complement. Step 3 above is checking that you are cutting this strip in exactly the right places.

The registers you will actually set

Start with the values below, then read the register map for each one until you can say what every bit does. Typical starting points for at 250 samples per second: CONFIG1 sets the data rate; CONFIG2 controls the test signal; CONFIG3 turns on the internal reference buffer and the bias amplifier; each CHnSET sets that channel’s to 24, connects it to a normal input, and connects its negative side to the SRB2 reference pin. The exact hexadecimal values are in the and in the , and copying them without reading the map is how mysterious behaviour happens later.

Where this leads

The phantom head gives you known signals to measure your board against. The characterization report is where the numbers go. And the explainers on amplifiers, conversion, noise, and safety each explain a design decision you just made.

Recall
What is the first thing to do after powering an ADS1299 board, and why?
Read the ID register over SPI (expect 0x3E). Until that works, nothing else can be debugged; it validates power, SPI wiring, mode, and reset.
Recall
Why validate with the internal test signal before connecting electrodes?
It is a known-amplitude square wave routed to every channel, so it checks SPI framing, sign handling, byte order, and voltage scaling all at once with no biological uncertainty.
Recall
Why does 24 bits not mean 24 bits of accuracy here?
At gain 24 one step is about 22 nV but the chip's own noise is around 1 µV, so the last several bits are noise. Effective resolution is what the noise floor allows.